This application relies from priority upon Korean Patent Application No. 1999-47959, filed on Nov. 1, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to semiconductors memory devices, and more particularly to a nonvolatile semiconductor memory device, which stores information of plural bits per cell.
Non-volatile integrated circuit memory devices can be classified into the following categories: mask ROMs; EPROMs; EEPROMs; and flash-EEPROMs. Among these memory devices, flash-EEPROMs have recently been discussed as permanent memories for personal computers in that they can achieve an electrical conversion of information while erasing stored data in a flash.
In conventional non-volatile memory devices, memory cells can take one of two information storing states, namely, the xe2x80x9cONxe2x80x9d state and xe2x80x9cOFFxe2x80x9d state. One bit of information is defined by the ON or OFF state of a respective memory cell. In order to store data of N bits (N: a natural number of 2 or greater) in the conventional memory devices mentioned above, N independent memory cells are necessary. When it is required to increase the number of bits of data to be stored in a memory device having one-bit memory cells, the number of such memory cells should increase correspondingly.
Information stored in a conventional one-bit memory cell is determined by the programmed status of the memory cell where programming is used to store the desired information in the memory cell. The information storing state of the memory cell is determined by the threshold voltage which is a minimum voltage to be applied between the gate and source terminals of the transistor included in the memory cell in order to switch the cell transistor to its ON state. In other words, memory cells have different information storing states in accordance with different threshold voltages thereof. In the case of EPROMs, EEPROMs, and flash-EEPROMs, a difference in the threshold voltage for cell transistors is obtained by storing different amounts of charge in the floating gates of the memory cells.
In particular, each memory cell transistor has two gates including upper and lower layers laminated on a channel region between source and drain regions. The upper gate is called a control gate. A charge storage portion is surrounded by an insulating material between the control gate and the channel region. This charge storage portion is called a floating gate. Accordingly, the state of information stored in each memory cell can be distinguished by the threshold voltage of that memory cell.
In order to read information stored in the memory cells of a memory device, it is necessary to check the information storing state of the programmed memory cells. To this end, signals required to read state information from a selected memory cell are applied to circuits associated with the selected memory cell by use of a decoder circuit. As a result, a current or voltage signal indicative of the stored information of the memory cell can be obtained on a bit line. In this way, the programmed information of a memory cell can be found by measuring the obtained current or voltage signal.
These memory devices can have a NOR-type or a NAND-type memory cell array structure depending on the connection of the memory cells to respective bit lines. In a NOR-type memory cell array, each memory cell is connected between a bit line and a ground line. In a NAND-type memory cell array, a plurality of memory cells are connected in series between a bit line and a ground line. A group of memory cells connected in series to one bit line along with selection transistors used to select those memory cells is called a string. The selection transistors may include a first transistor (or a string select transistor) arranged between the series-connected memory cells and the associated bit line, and a second transistor (or a ground select transistor) arranged between the series-connected memory cells and a ground line.
When reading information stored in a NAND-type memory device, a selected transistor in a selected string is switched to the ON state. In addition, a voltage higher than that applied to the control gate of the selected memory cell is applied to the control gates of unselected memory cells. As a result, the unselected memory cells have a low equivalent resistance as compared to the selected memory cell. The magnitude of the current flowing through the string from the associated bit line thus depends on the information stored in the selected memory cell of the string. The voltage or current corresponding to the information stored in each selected memory cell is sensed by a sensing circuit which is generally known as a sense amplifier.
Many schemes have been proposed to increase the information storage capacity of memory devices without involving an increase in chip size. For example, information of at least two bits can be stored in each memory cell. Conventionally, a memory cell stores only one bit of information therein. However, when 2 bits of information are stored in one memory cell, this memory cell is programmed with either xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d or xe2x80x9c11xe2x80x9d. Accordingly, a memory device can store twice the information with the same number of memory cells as compared to a memory device wherein only one bit is stored in a memory cell. When storing 2 bits per memory cell, a multi-state memory device is provided wherein the threshold voltage of each memory cell can be programmed to have one of four different values. Because the memory capacity per memory cell is doubled, the chip size can be reduced while providing the same memory capacity. As the number of bits stored per memory cell increases, the data storage capacity of the multi-state memory device increases.
FIG. 1 is a circuit diagram showing a conventional memory device wherein two bits of information per memory cell are stored using a NAND-type flash-EEPROM cells. The memory device in FIG. 1 is disclosed in U.S. Pat. No. 5,768,188 under the title of xe2x80x9cMULTI-STATE NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR DRIVING THE SAMExe2x80x9d, which is herein incorporated by reference.
The memory device disclosed in the ""188 patent includes two memory cell strings each having a plurality of series-connected memory cells. Two bit lines, associated with respective memory cell strings, are illustrated wherein these bit lines belong to different groups. As will be understood by one having skill in the art, larger numbers of memory cell strings and respective bit lines can be used. In FIG. 1, the memory cells of each string are labeled T1-2 to T1-5 or T1-8 to T1-11, respectively. A selection transistor, T1-1 or T1-7, is coupled between each string and the associated bit line. The selection transistor is selectively switched on to couple the associated string and bit line together. Another selection transistor, T1-6 or T1-12, is arranged between each string and a common source line CSL to selectively switch the connection between the string and common source line CSL. A depletion transistor, D1-1 or D1-2, is also coupled to each bit line to inhibit an application of high voltage.
A bit line selection transistor, S1-1 or S1-2, is also connected to each bit line. Each bit line selection transistor selects a respective bit line in response to a bit line selection signal, A9 or A9b. A signal line BLLVL is connected to each of the bit lines via transmission transistors TM1-1 and TM1-2. Each transmission transistor applies a signal BLLVL from the signal line BLLVL to the associated bit line in response to the bit line selection signals A9 and A9b applied thereto when the bit line is not selected. The signal BLLVL supplies a program inhibit voltage (for example, the supply voltage Vcc) to the unselected bit line during programming and reading operations while floating during the erase operation. A transistor T1-13 is also connected to the bit lines to supply static current to the selected bit line during the read operation. The memory device of FIG. 1 also includes latch-type sense amplifiers I1-1 and I1-2 (or I1-3 and I1-4) associated with each bit line. The sense amplifiers latch externally applied data during the programming operation, supply a voltage corresponding to the latched data to the associated bit line, and latch the data read during the read operation.
A plurality of transistors T1-17, T1-18, T1-19, T1-20, T1-21, T1-22 and T1-23 are provided, and these transistors invert or maintain latch states of the sense amplifiers in accordance with a bit line level selected during the reading operation. This function is controlled by latch enable signals xcfx86V2, xcfx86V1 and xcfx86R1. These latch enable signals are enabled in the form of a pulse at the point in time when an inversion in latch state is required after a predetermined time has elapsed since the beginning of the reading operation. A transistor T1-15 is also connected to the bit lines. The transistor T1-15 initializes the latches just before the execution of the read operation while maintaining the bit lines at a ground voltage state. The transistor T1-15 is controlled by a signal DCB. Transistors T1-14 and T1-16 are coupled to respective bit lines. These transistors T1-14 and T1-16 turn on when the programming operation is executed, thereby transmitting the latched data to the respective bit lines. The transistors T1-14 and T1-16 are respectively controlled by control signals PGM1 and PGM2.
FIG. 2 shows a threshold voltage distribution of a memory cell according to programmed data. As shown in FIG. 2, a programmed memory cell has one of a threshold voltage distribution (indicating 2-bit data of xe2x80x9c11xe2x80x9d) lower than xe2x88x922.0V, a threshold voltage distribution (indicating 2-bit data of xe2x80x9c10xe2x80x9d) between 0.4V to 0.8V, a threshold voltage distribution (indicating 2-bit data of xe2x80x9c01xe2x80x9d) between 1.6V to 2.0V, and a threshold voltage distribution (indicating 2-bit data of xe2x80x9c00xe2x80x9d) between 2.8V to 3.2V. Data can be stored in four different states in one memory cell on the basis of such threshold voltage distributions.
Referring to FIGS. 3 and 4, waveforms of signals associated with the programming and program verifying operations are illustrated. The program cycle includes a programming operation, in which electrons are injected into floating gates of memory cells, and a program verifying operation, in which it is verified whether or not each programmed memory cell has a desired threshold voltage. The programming and program verifying operations are repeated until all the selected memory cells have desired threshold voltages. The number of times these operations are repeated may be limited to an appropriate value internally determined in the memory device. In order to execute a program utilizing Fowler Nordheim tunneling in a selected memory cell, a high voltage as a predetermined program voltage (for example, 14 to 19V) is applied to the gate of the cell while the channel of the cell is maintained at the ground voltage level.
Accordingly, a relatively strong electric field is exerted between the floating gate and channel. By virtue of such an electric field, a tunneling occurs between the floating gate and channel through an oxide film formed between the floating gate and channel. Electrons existing in the channel thus migrate toward the floating gate, so that these electrons accumulate in the floating gate. The accumulation of electrons in the floating gate results in an increase in the threshold voltage of the cell. In the case of a memory device consisting of a plurality of data cells, programming operations for the data cells are not individually carried out, but simultaneously carried out. However, the memory cells may require different threshold voltages, namely, different programmed degrees. For this reason, it may be necessary to verify whether or not the memory cells reached their desired states, after the execution of one programming operation (program verification), and to execute another programming operation for incompletely programmed memory cells without affecting the completely programmed memory cells (program inhibition). These programming and program verifying operations are repeated until all the selected memory cells reach their desired threshold voltages. In the memory device of FIG. 1, only the half of memory cells connected to a selected word line is programmed as discussed above.
The program operation and the program verification operation according to the prior art will be described with reference to the timing diagram in FIG. 3. As well known to ones skilled in the art, before the program operation, all memory cells have a negative threshold voltage by an erase scheme, which is disclosed in U.S. Pat. No. 5,841,721 under the title of xe2x80x9cMULTI-BLOCK ERASE AND VERIFICATION IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREOFxe2x80x9d.
When one of two bit lines is selected in accordance with the bit line selection signals A9 and A9b, the supply voltage Vcc from the line BLLVL is applied to the unselected bit line, thereby inhibiting the memory cells associated with the unselected bit line but connected to the selected word line from being programmed. This programming inhibit technique including the application of a supply voltage to unselected bit lines will be understood by those having skill in the art.
Data to be programmed is loaded at latches Q2 and Q1 associated with the selected bit line BL1. Assume that data of xe2x80x9c00xe2x80x9d is loaded on the latches Q2 and Q1. Under this condition, if a first program cycle (a) commences, a signal PGM1 for selecting the latch Q1 transitions from a logic low level to a logic high level. Thus, the select bit line BL1 has a ground voltage level through a transistor T1-16. A high voltage is applied to a word line to which a selected memory cell is connected. After a time elapses, there is performed the program verification operation for verifying whether the selected memory cell is programmed up to a desired threshold voltage (for example, 0.4V to 0.8V).
When a sensing operation for program verification is executed, signals PGM1, PGM2 and PGM3 are maintained at a logic low level, respectively. If the selected memory cell is not programmed sufficiently, the bit line BL1 continues to be maintained at the ground voltage level as a result of the sensing operation. At this time, since logic states of the selected bit line BL1 and the latch Q1 are at a logic low level, transistors T1-19 and T1-20 are turned off. Thus, as illustrated in FIG. 3, a logic state of the latch Q1 is not inverted even if a latch activation signal xcfx86V1 is activated with a pulse form in a program verification period. The program operation and the program verification operation related to the latch Q1 are iterated by a predetermined program frequency or until the selected memory cell is sufficiently programmed. After the first program cycle (a) is ended, the selected memory cell has a threshold voltage distribution of 0.4V to 0.8V corresponding to xe2x80x9c10xe2x80x9d, as illustrated in FIGS. 6c and 6d. 
If a second program cycle (b) of FIG. 3 commences, a signal PGM2 for selecting the latch Q2 having xe2x80x980xe2x80x99 transitions from a logic low level to a logic high level. The selected bit line BL1 has the ground voltage level through a transistor T1-14. A high voltage is applied to the selected word line to which the selected memory cell is connected. After a time elapses, there is executed the program verification operation for verifying whether the selected memory cell is programmed up to a desired threshold voltage (for example, 1.6V to 2.0V).
When a sensing operation for program verification is executed, the signals PGM1, PGM2 and PGM3 are maintained at a logic low level, respectively. If the selected memory cell is programmed sufficiently, the bit line BL1 continues to be maintained at the supply voltage level as a result of the sensing operation, to thereby turn on a transistor T1-17. If a latch activation signal xcfx86V2, as illustrated in FIG. 3, is activated with a pulse form in a program verification period of the second program cycle (b), a logic state of the latch Q2 is inverted into xe2x80x9c1xe2x80x9d from xe2x80x9c0xe2x80x9d. On the other hand, if the selected memory cell is not programmed sufficiently, the selected bit line BL1 is maintained at the ground voltage level, thus the state of the latch Q2 is not inverted. In this case, the program operation and the program verification operation associated with the latch Q2 are iterated by a predetermined program frequency or until the selected memory cell is sufficiently programmed. After the second program cycle (b) is ended, the selected memory cell has a threshold voltage distribution of 1.6V to 2.0V corresponding to xe2x80x9c01xe2x80x9d, as illustrated in FIGS. 6c and 6d. 
Finally, if a third program cycle (c) of FIG. 3 commences, the signal PGM1 for selecting the latch Q1 having xe2x80x980xe2x80x99 transitions from a logic low level to a logic high level. The selected bit line BL1 has the ground voltage level through a transistor T1-16. A high voltage is applied to the selected word line to which the selected memory cell is connected. After a time elapses, there is executed the program verification operation for verifying whether the selected memory cell is programmed up to a desired threshold voltage (for example, 2.8V to 3.2V).
When a sensing operation for program verification is executed, the signals PGM1, PGM2 and PGM3 are maintained at a logic low level, respectively. If the selected memory cell is programmed sufficiently, the bit line BL1 continues to be maintained at the supply voltage level as a result of the sensing operation, to thereby turn on a transistor T1 -17. At this time, since the state of latch Q2 is xe2x80x9c1xe2x80x9d, the transistor T1-20 is turned on. Thus, if the latch activation signal xcfx86V1, as illustrated in FIG. 3, is activated with a pulse form in a program verification period of the third program cycle (c), a logic state of the latch Q1 is inverted to xe2x80x9c1xe2x80x9d from xe2x80x9c0xe2x80x9d. After the third program cycle (c) is ended, the selected memory cell has a threshold voltage distribution of 2.8V to 3.2V corresponding to xe2x80x9c00xe2x80x9d, as illustrated in FIGS. 6c and 6d. 
In the case that data of xe2x80x9c01xe2x80x9d is loaded on the latches Q2 and Q1, a program operation and a program verification operation are as follows. First, if a first program cycle (a) commences, the signal PGM1 for selecting the latch Q1 transitions from a logic low level to a logic high level. Thus, the select bit line BL1 has a supply voltage level through a transistor T1-16. Since the bit line BL1 is maintained at the supply voltage level of a program inhibition state, the selected memory cell is program-inhibited during the first program cycle (a). As a result, after the first program cycle (a), a threshold voltage of the selected memory cell is maintained with an erase state, that is, in a threshold voltage distribution of xe2x88x923V to xe2x88x922V corresponding to xe2x80x9c11xe2x80x9d.
If a second program cycle (b) of FIG. 3 commences, the signal PGM2 for selecting the latch Q2 having xe2x80x980xe2x80x99 transitions from a logic low level to a logic high level. The selected bit line BL1 has the ground voltage level through a transistor T1-14. A high voltage is applied to the selected word line to which the selected memory cell is connected. After a time elapses, there is executed the program verification operation for verifying whether the selected memory cell is programmed up to a desired threshold voltage (for example, 1.6V to 2.0V).
When a sensing operation for program verification is executed, the signals PGM1, PGM2 and PGM3 are maintained at a logic low level, respectively. If the selected memory cell is programmed sufficiently, the bit line BL1 continues to be maintained at the supply voltage level as a result of the sensing operation, to thereby turn on a transistor T1-17. If a latch activation signal xcfx86V2, as illustrated in FIG. 3, is activated with a pulse form in a program verification period of the second program cycle (b), a logic state of the latch Q2 is inverted into xe2x80x9c1xe2x80x9d from xe2x80x9c0xe2x80x9d. On the other hand, if the selected memory cell is not programmed sufficiently, the selected bit line BL1 is maintained at the ground voltage level, thus the state of the latch Q2 is not inverted. In this case, the program operation and the program verification operation associated with the latch Q2 are iterated by a predetermined program frequency or until the selected memory cell is sufficiently programmed. After the second program cycle (b) is ended, the selected memory cell has a threshold voltage distribution of 1.6V to 2.0V corresponding to xe2x80x9c01xe2x80x9d, as illustrated in FIGS. 6c and 6d. 
Continuously, if a third program cycle (c) of FIG. 3 commences, the signal PGM1 for selecting the latch Q1 transitions from a logic low level to a logic high level. The selected bit line BL1 has the supply voltage level through a transistor T1-16. Since the selected bit line BL1 is maintained at the supply voltage level of a program inhibition state, the selected memory cell is program-inhibited during the third program cycle (c). As a result, after the third program cycle (c) is ended, the selected memory cell has a threshold voltage distribution of 1.6V to 2.0V corresponding to xe2x80x9c01xe2x80x9d, as illustrated in FIGS. 6c and 6d. 
In the case that data of xe2x80x9c11xe2x80x9d is loaded on the latches Q2 and Q1, since the selected bit line BL1 is maintained at the supply voltage level in each of the first, second and third program cycles (a, b and c), the selected memory cell is maintained at the erased state. That is, the selected memory cell has a threshold voltage distribution of xe2x88x923V to xe2x88x922V, as illustrated in FIGS. 5a and 5b. In the case that data of xe2x80x9c10xe2x80x9d is loaded on the latched Q2 and Q1, a state of the latch Q1 is inverted into xe2x80x9c1xe2x80x9d from xe2x80x9c0xe2x80x9d as described at the program operation of xe2x80x9c00xe2x80x9d. Thus, the selected memory cell is program-inhibited in the second and third program cycles (b and c). As a result, the selected memory cell has a threshold voltage distribution of 0.4V to 0.8V.
A variation of a threshold voltage distribution according to programmed data of a selected memory cell during the above-described program operation is illustrated in FIGS. 5 and 6. Referring to FIGS. 6a and 6b which show a threshold voltage variation of xe2x80x9c01xe2x80x9d, since the selected memory cell is program-inhibited in the first program cycle (a), a threshold voltage of the selected memory cell is shifted from a threshold voltage distribution of xe2x88x923V to xe2x88x922V to a threshold voltage distribution of 1.6V to 2.0V when the second program cycle (b) is performed. That is, a threshold voltage of the selected memory cell is shifted directly into a threshold voltage distribution of xe2x80x9c01xe2x80x9d from a threshold voltage distribution of xe2x80x9c11xe2x80x9d without being shifted into a threshold voltage distribution of xe2x80x9c10xe2x80x9d. For this, a time required to program data of xe2x80x9c01xe2x80x9d is longer than that of a memory cell to be programmed sequentially or gradually (for example, refer to a description for data of xe2x80x9c00xe2x80x9d). Therefore, as illustrated by a dot line in FIGS. 6a and 6b, a threshold voltage distribution (1.5V to 2.1V) of a memory cell to be programmed with xe2x80x9c01xe2x80x9d is widened as compared with a desired threshold voltage distribution (1.6V to 2.0V), thus a margin between threshold voltage distributions is reduced. For example, there is reduced a margin between a threshold voltage distribution corresponding to xe2x80x9c10xe2x80x9d and a threshold voltage distribution corresponding to xe2x80x9c01xe2x80x9d, or a margin between a threshold voltage distribution corresponding to xe2x80x9c01xe2x80x9d and a threshold voltage distribution corresponding to xe2x80x9c00xe2x80x9d. This causes a read fail.
It is therefore an object of the invention to provide a nonvolatile semiconductor memory device which is capable of constantly maintaining a margin between threshold voltage distributions after programming.
It is another object of the invention to provide a nonvolatile semiconductor memory device which makes a threshold voltage of a memory cell sequentially shifted into a threshold voltage corresponding to each program data when programming the memory cell up to a desired threshold voltage.
This and other objects, advantages and features of the present invention are provided by flash memory device that comprises a storage circuit for storing information (for example, two-bit data) to be programmed to a memory cell and a program data judging circuit for judging logic states of data bits stored in the storage circuit. The program data judging circuit judges whether at least one of the data bits stored in the storage circuit indicates a program of the memory cell, and sets a bit line with a program voltage (for example, a ground voltage level) or with a program inhibition voltage (for example, a supply voltage level) according to the judgment result.
By this memory device, the memory cell is able to be programmed with a desired threshold voltage at each program cycle regardless of logic states of data bits stored in the storage circuit.